一种锁相频率合成系统的设计  

Design of a Phase-Locked Loop(PLL) Frequency Synthesizer System

作　　者：葛海波[1] 王海潼[2] 郑燕[1] 

机构地区：[1]西安邮电学院电信系,西安710061 [2]西安武警工程学院通信工程系,西安710086

出　　处：《电讯技术》2008年第1期44-46,共3页Telecommunication Engineering

基　　金：陕西省自然科学基础研究计划资助项目(2005F09)

摘　　要：描述了以MC145152和MC1648芯片为核心，采用锁相频率合成技术来实现电压控制LC振荡器的设计思路、方法及指标测试。本系统可以产生高稳定度的正弦信号，输出频带在5—25MHz范围内，并实时显示；输出频率的稳定度达到10^-3以上。该系统在通信领域有广泛的应用前景。This paper describes the design ideas, methods and specification tests of a voltage- controlled LC oscillator which is based on MC145152 and MC1648 chips, and realized by adopting phase- lockod loop（PLL） frequency synthesizing technology. This system can produce high stable sine signals and the output bands are in 5 - 25 MHz, and are real - time displayed. The output frequency stability is more than 10^-3. It will find wide application in the field of communications.

关 键 词：压控振荡器 频率合成 锁相环 

分 类 号：TN74[电子电信—电路与系统]