Fast-Lock Low-Jitter PLL with a Simple Phase-Frequency Detector  

一个简单鉴频鉴相器结构实现的快速锁定低抖动锁相环(英文)

作　　者：陈莹梅[1] 王志功[1] 章丽[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《Journal of Semiconductors》2008年第1期88-92,共5页半导体学报（英文版）

基　　金：国家高技术研究发展计划资助项目(批准号:2006AA01Z239)~~

摘　　要：A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.用简单的鉴频鉴相器结构实现了一个快锁定低抖动的锁相环.鉴频鉴相器仅仅由两个异或门组成,它可以同时获得低抖动和快锁定的性能.锁相环中的电压控制振荡器由四级环形振荡器来实现,每级单元电路工作在相同的频率,并提供45°的相移.芯片用0.18μmCMOS工艺来实现.PLL输出的中心频率为5GHz,在偏离中心频率500kHz处,测量的相位噪声为-102.6dBc/Hz.锁相环的捕获范围为280MHz,RMS抖动为2.06ps.电源电压为1.8V时,功耗仅为21.6mW(不包括输出缓冲).

关 键 词：phase locked loop phase-frequency detector voltage-controlled oscillator JITTER locking time 

分 类 号：TN763.3[电子电信—电路与系统]