基于3-DES算法的FPGA加密应用  

An implementation of FPGA security based on 3-DES algorithm

作　　者：李骞[1] 汪学刚[1] 李汉钊[1] 

机构地区：[1]电子科技大学电子工程学院,四川成都610054

出　　处：《电子技术应用》2008年第1期132-134,共3页Application of Electronic Technique

摘　　要：阐述了一种针对SRAM工艺FPGA的加密保护方案,并给出了主要模块的实现结构。该方案应用当前流行的3-DES算法对校验数据加密,可靠性高,占用资源少,具有较高的实际应用价值。This paper introduces an implementation to solve the securty problem of SRAM-based FPGA and presents the frame of the main modules.In this system the popular algorithm of Triple-DES has been applied to encrypt the data.The method has good authenticity and small consumption of resources. It can be widely used in practice.

关 键 词：DES 3-DES FPGA加密 CPLD 

分 类 号：TP332.1[自动化与计算机技术—计算机系统结构] TP393.08[自动化与计算机技术—计算机科学与技术]