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作 者:王峻松[1] 朱潇挺[1] 任腾龙[1] 洪志良[1]
机构地区:[1]复旦大学专用集成电路与系统国家重点实验室,上海201203
出 处:《微电子学与计算机》2008年第1期112-115,119,共5页Microelectronics & Computer
摘 要:改进了1-WIRE总线以提高其寄生供电容量,设计了自适应上拉电路,以电压监测和栅压自举开关为关键部件组成了寄生受电电路,从而把1-WIRE的寄生供电容量由5μA提升至平均值大于1mA,峰值10mA。新的总线主设备与目前广泛使用的的1-WIRE从设备可以向下兼容。采用TSMC0.25μm标准数字CMOS工艺设计了原型电路,仿真结果表明,电路性能满足设计要求,系统改进可行。This paper designed an adaptive pull - up circuit in the bus master of 1 - WIRE system and a parasite power supply circuit based on voltage monitor and boot - strapped CMOS switch in the bus slave to increase the parasite power supply capability from 5μA to 1mA average and 10mA peak, and the proposed bus master was backward compliant with the traditional 1 - WIRE slave devices. The prototype circuit was developed, and it was verified by simulation in TSMC 0.25μm Logic CMOS technologies. The circuit satisfied the new specification very well, which assured the feasibility of the proposed bus.
分 类 号:TN492[电子电信—微电子学与固体电子学]
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