一种降低流水化指令缓冲存储器泄漏功耗的设计方法(英文)  

A Low-Leakage Pipelined Instruction Cache Design

作　　者：孙含欣[1] 王箫音[1] 佟冬[1] 程旭[1] 

机构地区：[1]北京大学微处理器研究开发中心,北京100871

出　　处：《北京大学学报（自然科学版）》2008年第1期55-61,共7页Acta Scientiarum Naturalium Universitatis Pekinensis

基　　金：国家"863"计划(2004AA1Z1010)资助项目

摘　　要：流水化的指令缓冲存储器通常被用于高频率处理器中,以提高取指带宽。然而,在以往的研究工作中,对流水化指令缓冲存储器的泄漏功耗问题关注较少。在工作中发现流水化的指令缓冲存储器较之传统的指令缓冲存储器能够更好地提供降低泄漏功耗的机会。通过这一观察,提出根据取指地址的要求来动态管理指令缓冲存储器中行的活动——仅仅使需要访问的行处于正常活动状态,而其他行均被控制在低电压模式下,从而大幅度降低这些行的泄漏功耗。通过模拟评测发现,该方法使流水化的指令缓冲存储器的泄漏功耗降低了77.3%,而处理器的性能损失仅为0.32%。Pipelined level one instruction cache （PILl） has been proposed to improve instructian fetch bandwidth in high frequency processor. However, few researches in the literature have focused on reducing the leakage power in PILl. Here, the authors observe that the PILl structure naturally lends itself to provide inherent leakage power saving opportunities. Based on this observation, the authors propose to manage cache line activities according to the demand of the fetch address, which activates only the requested line and keeps others in low-voltage mode, thereby saving leakage power effectively. Simulation results demonstrate that the PILl leakage power is reduced by an average of 77.3 %. Meanwhile, the performance degradation is only 0.32 % and no timing overhead is induced.

关 键 词：泄漏功耗 流水化指令缓冲存储器 动态电压调节 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]