DVB-H中高效低延迟RS译码器的设计  

Design of High-efficient and Low-latency RS Decoder for DVB-H

作　　者：刘祺[1] 陈佳品[1] 李振波[1] 

机构地区：[1]上海交通大学微纳科学技术研究院,上海200030

出　　处：《电视技术》2008年第1期39-41,共3页Video Engineering

基　　金：国家自然科学基金资助项目(60475037;10477013);教育部高等学校博士点基金资助项目(20060248057)

摘　　要：针对DVB-H中RS(255,191)码译码器消耗硬件多、延迟时间长等缺点,通过采用脉动式阵列及新的修正Euclidean迭代算法实现结构,并用查找表ROM取代常规求逆电路,设计了一种高效低延迟的RS(255,191)译码器。该译码器符合DVB-H标准的性能要求,同时缩小了电路规模,缩短了译码延迟时间。In allusion to the hardware complexity and long time delay of RS（255,191） decoder for DVB-H, several methods are used to design a decoder with high-efficient and low-latency. The methods include the usage of systolic arrays and modified Euclidean iterative algorithm, and the replacement of general inversing circuit by book-up-table ROM. The new decoder does not only meet the performance requirements of DVB-H, but also reduces the circuit scale and shortens the time delay.

关 键 词：脉动式阵列 修正Euclidean算法 查找表 

分 类 号：TN919.32[电子电信—通信与信息系统]