基于TTA体系结构的嵌入式协处理器的设计与实现  

The Design and Implementation of the Embedded Coprocessor Based on TTA

作　　者：赖明澈[1] 戴葵[1] 陆洪毅[1] 岳虹[1] 王志英[1] 

机构地区：[1]国防科学技术大学计算机学院

出　　处：《计算机科学》2008年第2期293-297,共5页Computer Science

基　　金：自然科学基金支持(No.60173040;No.90407022)

摘　　要：本文基于TTA结构提出了一种嵌入式协处理器体系结构,并完成了其VLSI设计与实现。该协处理器具有双Cluster的运算内核,能够高效地支持多媒体应用中的数据密集型计算。为了充分发挥协处理器工作效率,本文还设计了具有流缓冲代理特征的流存储子系统,通过实现数据流存储访问机制以及计算资源与片外存储之间的低耦合结构,提高访存带宽。最后,基于该嵌入式协处理器,本文在0.18μmCMOS工艺下实现了一款多核SoC芯片,其工作主频为300MHz,实测功耗为910mW。A novel embedded coprocessor based on the Transport Triggered Architecture is presented in this paper. The coprocessor is consisted of two powerful arithmetic clusters, and good at exploiting the data parallelism in the computation intensive multimedia applications. To improve the efficiency, the coprocessor also designs the stream memory system with the characteristic of the stream buffer proxy, especially uses the decoupled architecture and the stream access mechanism to enhance the access bandwidth. Then, a heterogeneous multiprocessor SoC chip involving the coprocessor is implemented using 0. 18/zm CMOS process, which can operate at 300MHz and consume about 910mW.

关 键 词：传输触发体系结构 协处理器 代理缓冲 

分 类 号：TP332[自动化与计算机技术—计算机系统结构] TP301[自动化与计算机技术—计算机科学与技术]