Low-power clock-less hardware implementation of the rijndael S-box for wireless sensor networks  

作　　者：ZENG Yong-hong ZOU Xue-cheng LIU Zheng-lin LEI Jian-ming 

机构地区：[1]Research Center for VLSI and Systems, Department of Electronic Scienceand Technology, Huazhong University of Science and Technology,Wuhan 430074, China

出　　处：《The Journal of China Universities of Posts and Telecommunications》2007年第4期104-109,共6页中国邮电高校学报（英文版）

基　　金：the Hi-Tech Research and Development Program of China（2006AA01Z226）;the Scientific Research Foundation of Huazhong University of Science and Technology（2006Z001B);the Natural Science Foundation of Hubei（2006ABA080）.

摘　　要：The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor networks （WSN）. The design challenges for an efficient WSN mainly lie in two issues： power and security. The Rijindael algorithm is a candidate algorithm for encrypting data in WSN. The SubByte （S-box） transformation is the main building block of the Rijindael algorithm. It dominates the hardware complexity and power consumption of the Rijindael cryptographic engine. This article proposes a clock-less hardware implementation of the S-box. In this S-box, l） The composite field arithmetic in GF（（2^4））2 was used to implement the compact datapath circuit; 2） A high-efficiency latch controller was attained by utilizing the four-phase micropipeline. The presented hardware circuit is an application specific integrated circuit （ASIC） on 0.25 μm complementary mental oxide semiconductor （CMOS） process using three metal layers. The layout simulation results show that the proposed S-box offers low-power consumption and high speed with moderate area penalty. This study also proves that the clock-less design methodology can implement high- performance cryptographic intellectual property （IP） core for the wireless sensor node chips.The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor networks （WSN）. The design challenges for an efficient WSN mainly lie in two issues： power and security. The Rijindael algorithm is a candidate algorithm for encrypting data in WSN. The SubByte （S-box） transformation is the main building block of the Rijindael algorithm. It dominates the hardware complexity and power consumption of the Rijindael cryptographic engine. This article proposes a clock-less hardware implementation of the S-box. In this S-box, l） The composite field arithmetic in GF（（2^4））2 was used to implement the compact datapath circuit; 2） A high-efficiency latch controller was attained by utilizing the four-phase micropipeline. The presented hardware circuit is an application specific integrated circuit （ASIC） on 0.25 μm complementary mental oxide semiconductor （CMOS） process using three metal layers. The layout simulation results show that the proposed S-box offers low-power consumption and high speed with moderate area penalty. This study also proves that the clock-less design methodology can implement high- performance cryptographic intellectual property （IP） core for the wireless sensor node chips.

关 键 词：WSN rijindael algorithm S-BOX clock-less composite field arithmetic four-phase micropipeline 

分 类 号：TN4[电子电信—微电子学与固体电子学] TP309[自动化与计算机技术—计算机系统结构]