基于VMT的DDR-SDRAM控制器功能验证  

Functional Verification Based on VMT for DDR-SDRAM Controller

作　　者：高夫[1] 杜学亮[1] 金西[1] 

机构地区：[1]中国科技大学物理系微电子学教研室,合肥230026

出　　处：《计算机工程》2008年第4期263-265,274,共4页Computer Engineering

摘　　要：介绍了一种基于验证模型技术(VMT)的DDR-SDRAM控制器的功能验证方案。该方案完成了DDR-SDRAM控制器对DDR-SDRAM模型的读写以及AHB 2.0协议的兼容性验证。VMT的使用加快了验证平台的搭建和验证用例的编写。通过分析自动校对结果、仿真波形和覆盖率报告,实现控制器功能验证的快速收敛。FPGA原型验证进一步证明了该方案的可行性。This paper introduces a solution for functional verification of DDR-SDRAM controller. The solution, based on VMT, completes the writing ＆ reading operations happened between DDR-SDRAM controller and DDR-SDRAM model. The compatibility with AHB 2.0 specification is also verified. Using VMT accelerates building the testbench and writing the tastcases. Fast convergence of functional verification is implemented by analyzing the auto-check results, simulation waveform and coverage report. The verification based on FPGA proves the feasibility of the solution.

关 键 词：验证模型技术 DDR—SDRAM控制器 VIP技术 

分 类 号：TP31[自动化与计算机技术—计算机软件与理论]