基于交易级建模的ATA控制器功能验证方法研究  

Functional verificationenvironment for ATA controllerbased ontransactionlevel modeling

作　　者：李潮激[1] 张珩[1] 沈海华[1] 

机构地区：[1]中国科学院计算技术研究所系统结构重点实验室

出　　处：《计算机工程与设计》2008年第2期261-263,273,共4页Computer Engineering and Design

基　　金：国家自然科学基金项目(60603049)

摘　　要：交易级建模技术适用于构建大规模电路系统的功能验证平台。结合C++天生的类继承机制和SystemC的接口通道机制,基于该建模技术的ATA控制器验证平台成功实现了随机化的交易级验证,降低了设计模块间通信的复杂度,结构上具有良好的可扩展性和可重用性。着重阐述该验证平台中抽象通道与适配器的通用设计方法,提出了一种基于面向对象技术的创新的验证平台设计模式,并分析了交易级建模和RTL建模之间的区别以及交易级建模技术在提高验证效率上的优势。Transaction level modeling is a new methodology on building functional verification environment for large scale circuit design. Based on the object-oriented technology of C＋＋ and the port-channel mechanism offered by SystemC, a random-biased functional verification environment for ATA controller has been successfully completed in transaction level. Complexity of communication between modules is reduced by using channels and interfaces. A simple yet effective design pattern is developed during the testbench evolution, and the architecture is easily adapted to similar testbench designs. The difference between the TLM and RTL modeling is described. The benefits of transaction level modeling are shown by experimental results.

关 键 词：交易级建模 功能验证 设计模式 重用性 覆盖率 

分 类 号：TN407[电子电信—微电子学与固体电子学]