Chip Multithreaded Consistency Model  

作　　者：李祖松 郇丹丹 胡伟武 唐志敏 

机构地区：[1]Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100080,China

出　　处：《Journal of Computer Science & Technology》2008年第2期298-304,F0003,共8页计算机科学技术学报（英文版）

基　　金：Supported by the National High Technology Development 863 Program of China(Grant Nos.2007AA01Z114, 2006AA010201);the National Natural Science Foundation of China(Grant Nos.60703017, 60736012, 60325205, 60673146, 60603049);the National Grand Fundamental Research 973 Program of China(Grant Nos.2005CB321601, 2005CB321603);Beijing Natural Science Foundation(Grant No.4072024).

摘　　要：Multithreaded technique is the developing trend of high performance processor. Memory consistency model is essential to the correctness, performance and complexity of multithreaded processor. The chip multithreaded consistency model adapting to multithreaded processor is proposed in this paper. The restriction imposed on memory event ordering by chip multithreaded consistency is presented and formalized. With the idea of critical cycle built by Wei-Wu Hu, we prove that the proposed chip multithreaded consistency model satisfies the criterion of correct execution of sequential consistency model. Chip multithreaded consistency model provides a way of achieving high performance compared with sequential consistency model and easures the compatibility of software that the execution result in multithreaded processor is the same as the execution result in uniprocessor. The implementation strategy of chip multithreaded consistency model in Godson-2 SMT processor is also proposed. Godson-2 SMT processor supports chip multithreaded consistency model correctly by exception scheme based on the sequential memory access queue of each thread.Multithreaded technique is the developing trend of high performance processor. Memory consistency model is essential to the correctness, performance and complexity of multithreaded processor. The chip multithreaded consistency model adapting to multithreaded processor is proposed in this paper. The restriction imposed on memory event ordering by chip multithreaded consistency is presented and formalized. With the idea of critical cycle built by Wei-Wu Hu, we prove that the proposed chip multithreaded consistency model satisfies the criterion of correct execution of sequential consistency model. Chip multithreaded consistency model provides a way of achieving high performance compared with sequential consistency model and easures the compatibility of software that the execution result in multithreaded processor is the same as the execution result in uniprocessor. The implementation strategy of chip multithreaded consistency model in Godson-2 SMT processor is also proposed. Godson-2 SMT processor supports chip multithreaded consistency model correctly by exception scheme based on the sequential memory access queue of each thread.

关 键 词：computer architecture GODSON-2 MULTITHREADING memory consistency model event ordering 

分 类 号：TN402[电子电信—微电子学与固体电子学]