针对JTAG调试的RTL验证环境设计原理  

Design of RTL verification environment for JTAG debugger

作　　者：韩可[1] 邓中亮[1] 施乐宁[2] 吕良[1] 

机构地区：[1]北京邮电大学电子工程学院,北京100876 [2]北京航空航天大学电子信息工程学院,北京100083

出　　处：《电子测量技术》2008年第1期72-76,87,共6页Electronic Measurement Technology

摘　　要：以ARM7TDMI为例提出了一种在RTL仿真时即可进行JTAG调试的方法。利用该方法在RTL仿真时即可进行ARM的JTAG调试。首先详细分析了JTAG的边界扫描标准及工作原理,而后以ARM7TDMI为例分析了ARM的扫描链的设计原理及控制方法,从中给出了如何利用JTAG控制ARM7TDMI扫描链来完成ARM的行为控制。该方法还可以通过ARM的控制进而完成对SoC中其他模块的验证。通过该原理建立JTAG接口软仿真验证平台,可以在RTL仿真时验证ARM的JTAG调试功能以及SoC的初步测试。A method for puting up the RTL verification environment of the JTAG debugger is proposed by the example of ARM7TDMI. The debug of ARM through JTAG interface can be done in the RTL simulation. The JTAG standard and the ARM7TDMI scan chains are also analyzed in this paper. It gives the method to control the ARM7TDMI behavior by JTAG and the scan chains. An ARM7TDMI based verification plat is designed and it can verification the JTAG debugger function when the design is in the RTL phase.

关 键 词：JTAG ARM7TDMI 系统芯片 RTL验证 

分 类 号：TN74[电子电信—电路与系统]