基于性能的FPGA再设计过程中的工艺映射  

Performance-Based Technology Mappingin the Redesign of FPGA's

作　　者：张万鹏[1] 童家榕[1] 唐璞山[1] 

机构地区：[1]复旦大学电子工程系集成电路CAD实验室

出　　处：《微电子学》1997年第4期272-275,共4页Microelectronics

摘　　要：提出了－个基于性能的ＬＵＴ结构的ＦＰＧＡ再设计过程中的工艺映射算法。采用该算法不改变网络的拓扑结构，而是用特征函数以及时原布尔网络进行相应的约束实现电路的再设计，从而避免了在再设计过程中重新考虑电路的时延和布局布线结果，用于较大规模的电路有很好的实验结果。An algorithm for performance-based technology mapping in the redesign of FPGA 's. with look-up table (LUT)structure is presented. In the algorithm .characteristic functions are used . and a redesign based on restrictions on the original relation is performed. Since the topology of the boolean network has not been changed in the redesign .there is no need for reconsidering the circuit delay and the results of placement and routing. Excellent results have been achieved for larger scale circlets.

关 键 词：ASIC FPGA 工艺映射 IC CAD 

分 类 号：TN430.2[电子电信—微电子学与固体电子学]