一种基于新体系结构的空间固态记录器原型系统  

A Novel Architecture Prototype of Space Solid-State Recorder

作　　者：张科[1] 郝智泉[1] 王贞松[1] 

机构地区：[1]中国科学院计算技术研究所普适计算研究中心

出　　处：《电子学报》2008年第2期285-290,共6页Acta Electronica Sinica

摘　　要：为适应未来对地观测卫星系统对数据吞吐速率和通信带宽的增长需求,本文提出并实现了一种基于新体系结构的,由若干存储模块依靠高速串行互连构成的空间固态记录器原型系统.存储模块采用DDR SDRAM提高吞吐率,配置高速串行接口完成模块间互连,利用单数据总线、双地址总线的存储拓扑结构增加模块内部存储容量,并使用可编程逻辑器件FPGA管理和控制存储资源.同时,应用多层次通信接口协议保证通信链路质量.单模块存储容量可达8GB,访存带宽可达3.2GBps,物理通信带宽高达25Gbps.模块间的高速串行链路误码率可低于10-11.To meet the future demands of earth observation satellites,this paper presents a novel architecture and describe the implementation of a prototype named Space Solid-State Recorder with several Memory Modules （MMs） connected by high-speed serial links. The MM utilizes an FPGA and DDR SDRAM to boost throughput, and adopts a featured SDDA （Single-Data-bin, Donble-Address-bus） storage topology to manage and control these memory chips efficiently. Through higl-speed serial transceivers embedded in the FPGA chip,several MMs interconnect with each other to form the Space Solid-State Recorder. To ensure the quality of serial links, a multilayer commumicafion interface protocol stack that consists of a physical layer, link layer and message layer is propose. As a result,the MM can provide storage capacity of 8GB,and its memory bandwidth approaches 3.2GBps. Furthermore, the physical bandwidth of the communication interface can reach up to 25Gbps. Moreover,the bit error rate （BER） of the interface in Space Solid-State Recorder system is below 10^-11.

关 键 词：固态记录器 高速串行链路 存储模块 可编程逻辑器件FPGA DDR SDRAM存储控制器 

分 类 号：TP333[自动化与计算机技术—计算机系统结构] V447[自动化与计算机技术—计算机科学与技术]