基于映射表的寄存器文件设计以及编译器优化  

Mapping Table Based Register File Design and Compiler Optimization

作　　者：邓晴莺[1] 张民选[1] 

机构地区：[1]国防科学技术大学计算机学院,PDL,湖南长沙410073

出　　处：《电子学报》2008年第2期392-396,共5页Acta Electronica Sinica

基　　金：国家863高技术研究发展计划基金(No.2002AA110020);国家自然科学基金(No.60273069,No.60376018)

摘　　要：寄存器文件的设计在高性能处理器设计中十分重要,寄存器栈和寄存器栈引擎是提高其性能的重要手段.编译优化常常基于特定的体系机构以及目标机器.本文针对EDSMT微体系结构(基于IA-64的同时多线程体系结构)提出了一种新颖的基于映射表的寄存器机制——MTRM(Mapping Table-based Register Management),它通过映射表将连续的虚拟寄存器物理号映射到不连续的实际物理寄存器,并研究了编译器支持下的及时去配,实验结果表明该方案能有效提高性能.Register file design is very important in high perfonnance processor design. Register Stack and Register Stack Engine are effective ways to improve performance. Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. In this paper, we present our efforts to design and implement register file management raechanism MTRM （Mapping Table-based Register Management） on EDSMT, which is a kind of SMT architecture based on IA-64. MTRM assigns a Mapping Table for each thread to mapping their logic registers to physic registers, which adds a middle level into Itanium＇ s original rename mechanism. MTRM focused on supporting the effective sharing of registers in an EDSMT processor, using register renaming to permit multiple threads to share a single global register file. Existing hardware is effective at allocating physical registers;it has only limited ability to identify register deaUoeation points. Compile optimization is considered to deallocate dead registers, while Special Bit and Special Instruction are used as two effective ways. Simulation results indicate that these mechanisms call reduce register deaUocation ineffciencies;in particular,on small register files,the best of the schemes attains speedups of up to 2.2 for some applications,and 1.8 on average.

关 键 词：寄存器文件 同时多线程 EPIC 并行 编译优化 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]