基于开关运放的低功耗逐次逼近ADC设计  

Low-Power Successive Approximation ADC Design Using Switched-Opamp

作　　者：乔峻石[1] 李冬梅[2] 

机构地区：[1]清华大学微电子所,北京100084 [2]清华大学电子工程系,北京100084

出　　处：《半导体技术》2008年第3期252-256,共5页Semiconductor Technology

基　　金：国家自然科学基金资助项目(60475018);国家高技术研究发展计划资助项目(2006AA04A109)

摘　　要：基于UMC 0.18混合信号工艺,设计了一种低功耗逐次逼近ADC,重点考虑了功耗的优化和电路的改进,采用了开关运放技术,降低了传统缓冲器30%左右的能量消耗,同时比较器低功耗的设计也使该ADC节能的优点更加突出,同时比较器采用了失调校准技术,这样就能够满足10 bit精度的要求。在电源电压1.8 V、采样频率100 kHz的条件下,仿真得到该逐次逼近ADC信噪比为61.66 dB,而静态功耗仅为26μW。该设计的芯片版图面积为1 mm×1 mm。A low power successive approximation ADC was realized based on a 0.18 μm standard CMOS process, mainly considered the optimization of power consuption and the improvement of circuit. Switched- opamp was used in the ADC design, the power consumption of the buffer was reduced by 30 %. An auto zero comparator was specifically designed to achieve low power and low offset using offset calibration, it can meet the requirement of 10 bit. The simulation result shows that the ADC has signal-to-noise ratios of 61.66 dB and static power consumption of 26 μW with rail-to-rail input at supply voltage of 1.8 V, sampling rates of 100 kHz, die area is 1mm × 1 mm.

关 键 词：开关运放 逐次逼近ADC 低功耗比较器 失调校准 

分 类 号：TN423[电子电信—微电子学与固体电子学]