基于相位噪声分析的小型化24GHz数字锁相源设计  

Miniature 24GHz Digital Phase Locked Loop Frequency Generator Design Based on Phase Noise Analysis

作　　者：郑淑启[1] 沈秀英[2] 孙晓玮[1] 

机构地区：[1]中国科学院上海微系统与信息技术研究所 [2]华东师范大学电子系,上海200062

出　　处：《微波学报》2008年第1期61-64,共4页Journal of Microwaves

基　　金：上海市信息产业发展专项资金(123)

摘　　要：基于相位噪声分析方法仿真了微波锁相环,根据仿真结果成功设计制作了小型24GHz数字锁相环,总体电路尺寸仅2 cm×3.5 cm×4 cm。偏离24GHz载频1kHz处的相位噪声-67dBc/Hz,采用高性能的晶振会获得更优异的相位噪声指标。输出功率为7.9dBm,其长期稳定度与参考晶振的长期稳定度一致。测试结果表明:基于相位噪声分析的数字锁相频率源设计方法是可行的。该信号源可用于小型化多普勒雷达测速系统。Based on the method of phase noise analysis, this paper simulated the microwave phase locked loop （PLL）. The PLL circuit is designed and fabricated with the total dimension as small as 2cm × 3.5cm ×4cm. The measurement result of phase noise is -67dBc/Hz@ 1 kHz offset the 24GHz carrier. Better phase noise result can be obtained by utilizing a higher performance crystal oscillator. Its output power is 7.9dBm and the long term stability is the same as the crystal oscillator, Testing results indicate that the design method of digital PLL frequency generator based on the phase noise analysis is feasible. This generator can be utilized on miniature Doppler velocity measurement systems.

关 键 词：锁相环 相位噪声 小型化 

分 类 号：TN911.8[电子电信—通信与信息系统] TN702[电子电信—信息与通信工程]