一种基于FPGA的FIR滤波器实现结构  

A Novel Architecture of FIR Filter Based on FPGA

作　　者：何健标[1] 王宏远[1] 郭跃[1] 陈筱倩[1] 

机构地区：[1]华中科技大学电信系数字视频技术与通信研究所,湖北武汉430074

出　　处：《微电子学与计算机》2008年第3期47-50,共4页Microelectronics & Computer

摘　　要：提出了一种在FPGA中能灵活实现各种FIR滤波器的结构。该结构以使用流水线技术的高速乘法累加器(Multiple Accumulator,MAC)为核心,通过逻辑设计中时间-空间的互换,以最优的资源消耗来实现各种性能的FIR滤波器.最后以DVB-C系统中基带成形滤波器的设计实现为例与传统实现结构进行比较,结果表明此实现结构能灵活处理综合面积和速度的约束关系,具有更优的性价比.This paper proposes a novel architecture for implementing various FIR filters expediently in a FPGA chip. And the architecture, which utilizes high-speed pipelined multiple accumulators, can implement different FIR filters with lowest logic resource usage by considering area-speed tradeoffs. Besides, the baseband sharping filter in DVB-C is taken as example to show how to implement FIR filter with this architecture and compare with the traditional implementation architecture for FIR filter, and the result reveals that the restriction of synthesis between the area and speed can be much more efficiently optimized by using the proposed architecture.

关 键 词：FIR滤波器 FPGA 乘法累加器 基带成形 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]