高码率自适应Turbo编译码器的设计与FPGA实现  

Design and FPGA Realization of High Code-rate Adaptive Turbo Encoder and Decoder

作　　者：黄懿[1] 周兴建[2] 余金权[2] 阎鸿森[1] 

机构地区：[1]西安交通大学信息与通信工程系,西安710049 [2]中国西南电子技术研究所,成都610036

出　　处：《电讯技术》2008年第3期82-85,共4页Telecommunication Engineering

摘　　要：提出了一种高码率自适应Turbo编译码器的FPGA实现方案。在编码模块中采用特定参数的分组螺旋对称交织器,使编码器能通过删余构造高码率,且能通过相同的结尾比特使两个分量编码器的寄存器状态均归零。在SOVA译码模块中,各状态下路径的累积度量值的并行计算和可靠性值的并行更新使译码速度大大提高。仿真结果表明,该高码率自适应编译码器有良好的误码性能和较高的实用价值。A new FPGA realization scheme for high code - rate adaptive Turbo encoder/decoder is proposed. In encoding module, the block helix symmetric interleaver with specific parameters was used to construct high code - rate by puncturing and insure termination of both encoders by appending the same set of bits. In SOVA decoding module, parallel computation for the cumulative metric values of two candidate paths at each state and parallel update for the reliability values improve the decoding speed. The simulation result shows that the high code - rate adaptive encoder/decoder has good BER performance and can be put into practical use.

关 键 词：TURBO码 SOVA算法 分组螺旋对称交织器 删余 FPGA 

分 类 号：TN911.22[电子电信—通信与信息系统]