基于DSP Builder全数字接收机定时载波同步算法的实现  

Implementation of timing and carrier-phase recovery in all-digital receivers based on DSP Builder

作　　者：陈舒[1] 刘奇佳[2] 刘昌清[2] 赵克明[1] 

机构地区：[1]中国科学院中国遥感卫星地面站 [2]清华大学电子工程系,北京100084

出　　处：《中国科学院研究生院学报》2008年第2期238-243,共6页Journal of the Graduate School of the Chinese Academy of Sciences

摘　　要：讨论了全数字接收机中同步算法的设计与实现,给出了基于Gardner反馈环路的定时同步算法和基于数字Costas环的载波相位补偿算法的定点实现方案,并在Altera公司的DSP Builder上实现了该算法.计算机仿真和FPGA(Field Programmable Gate Array)实现都验证了其有效性,测试结果表明,该系统信噪比恶化小于1.5dB,时钟捕捉带大于±1%,载波频差捕捉带大于±4%.In this paper,the design and implementation of the synchronization algorithms in all-digital communication receivers are introduced.The fixed-point timing recovery algorithm based on the Gardner feedback loop approach and the carrier recovery algorithm using digital Costas loop are realized via Altera DSP Builder.Both the computer simulation and the FPGA realization demonstrate the validity of the algorithms.Results show that the realized system has good performance with the SNR degradation less than 1.5dB,the acquisition ranges of timing recovery and carrier recovery larger than ±1% and ±4%,respectively.

关 键 词：全数字接收机 GARDNER算法 数字COSTAS环 DSP BUILDER 

分 类 号：TN927.21[电子电信—通信与信息系统]