针对H．264去块滤波的实用结构设计  

Implemented architecture design of deblocking filter for H.264

作　　者：方健[1] 张丁[1] 徐红[2] 王匡[1] 

机构地区：[1]浙江大学信息与电子工程学系,浙江杭州310027 [2]浙江工业大学信息工程学院,浙江杭州310014

出　　处：《浙江大学学报（工学版）》2008年第3期460-465,共6页Journal of Zhejiang University：Engineering Science

基　　金：国家自然科学基金资助项目(90307002)

摘　　要：为了提高H.264去块滤波的性能,提出了一种实用的环路滤波设计结构.使用优化的滤波顺序,执行一个宏块的滤波运算只需要252个周期,待滤波数据缓冲从16×16宏块大小降低为4×4块大小.利用数据重用策略,滤波中间数据的存储空间从16×16宏块减小到4个4×4块.使用优化的流水设计,有效降低了去块滤波对总线的数据访问.使用0.18μm工艺,100 MHz下综合只需要14.2×103门.与以前的设计相比,该去块滤波结构具有更好的综合性能,而且硬件实现面积更小.在100 MHz频率下,该设计能够执行H.264高清视频应用的实时滤波处理.An implemented architecture of deblocking filter was proposed to improve the performance of deblocking filter in H. 264. With a novel filtering order, only 252 cycles were needed to perform the deblocking filter of a macroblock, consequently the unfiltered data storage was reduced to a 4 × 4 block instead of a whole 16×16 macroblock. According to the data reuse strategy, the intermediate data storage was also reduced from a whole 16×16 macroblock to four 4×4 blocks. With an optimized pipeline design, the data access to bus was reduced efficiently. The resulting design could achieve 100 MHz with only gate counts of 14.2×10a by using 0.18μm technology. Compared with former designs, the proposed deblocking filter architecture can achieve better performance with smaller hardware area. At 100 MHz, the proposed design can perform real-time deblocking filter for high definition video application of H. 264.

关 键 词：H.264/AVC 去块滤波 结构设计 

分 类 号：TN919.81[电子电信—通信与信息系统]