基于0．6μmCMOS工艺应用在高速ADC工作频率300MHz的高速电压比较器设计  

0.6 μm CMOS 300 MHz High-Speed Voltage Comparator Design for High-Speed ADC

作　　者：唐凯[1] 孟桥[1] 刘海涛[1] 

机构地区：[1]东南大学射频与光电集成电路研究所

出　　处：《电子器件》2008年第2期476-479,共4页Chinese Journal of Electron Devices

摘　　要：高速比较器是高速模数转换电路的关键环节。本文综合考虑了比较器的传输延时、失调电压等因素,分析了前置放大器和比较锁存电路的结构,在此基础上设计了一个基于CSMC0.6μmCMOS工艺、适合于高速ADC的高速电压比较器。仿真结果表明:比较器工作频率为300MHz以上,工作电流约为3.3mA,上升延时为993ps,下降延时为932ps,失调电压约为7.46mV。该比较器可以在高速模数转换电路中应用。High-speed comparator design is a key point in the high-speed ADC design. To consider the propagation delay, offset voltage and other factors, the structure of the preamplifier and compare-latch circuit is analyzed and a high-speed voltage comparator is designed. This circuit is designed on the basis of CSMC 0. 6μm CMOS process and 5.0 V power supply. The simulation result shows that the circuits can work in 300 MHz, with the working current 3.3 mA , rising time of 993 ps ,falling time of 932 ps and input offset voltage about 7. 46 mV. It can be used in high-speed ADC design.

关 键 词：高速模数转换器 高速比较器 传输延时 失调电压 

分 类 号：TN432[电子电信—微电子学与固体电子学]