高速FFT芯片设计及结构研究  

Design of a High Speed FFT Chip and Its Improved Structure

作　　者：黄宁[1] 朱恩[1] 荣瑜[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《电子器件》2008年第2期511-515,共5页Chinese Journal of Electron Devices

摘　　要：基于TSMC0.18μm CMOS工艺库,设计了一种高速FFT处理芯片,并对结构进行了研究和改进。系统采用时间抽取的快速傅里叶变换基2算法、流水线结构,对IEEE754单精度浮点数构成的复数进行处理。逻辑综合与版图综合后的报告显示系统的核面积(包含RAM和ROM)为3.61mm2。仿真结果表明,系统能够稳定工作在166.7MHz时钟下,且输出数据精度较高。本次设计的速度、精度及面积均达到了设计指标。A high speed FFT（fast fourier transform） chip with TSMC（Taiwan Semiconductor Manulacturing Company）0. 18 μm CMOS technology library is designed and the structure is also improved. The system which is based on FFT algorithm of Radix 2 and DIT（decimation in time） use pipelined architecture to operate complex number of IEEE 754 Std. single precision format. The report of logic and layout synthesis shows the core area （with ROM and RAM） of the system is 3.61 mm^2. The results of simulation demonstrate that the system can operate stably at 166.7 MHz with precisely output data. The speed, precision and area in this design totally meet the requirements.

关 键 词：快速傅立叶变换 蝶形运算 流水线 w因子 结构 FPGA 芯片 

分 类 号：TN402[电子电信—微电子学与固体电子学]