基于FPGA的板级BIST设计和实现策略  

Design for Board-level BIST and Its Realization Strategy Based on FPGA

作　　者：杜影[1] 赵文彦[1] 安佰岳[1] 

机构地区：[1]北京航天测控技术开发公司,北京100037

出　　处：《计算机测量与控制》2008年第3期389-391,共3页Computer Measurement &Control

基　　金：总装备部预研项目(51317040204)

摘　　要：为解决复杂电路板的测试问题,边界扫描、内建自测试等可测性设计技术相继发展,针对目前板级可测性设计发展状况,提出了基于FPGA的板级BIST设计策略;通过阐述存储器模块、逻辑模块和模拟模块三大部分的BIST设计,说明了基于FPGA进行板级模块BIST设计的灵活性和优势;最后,给出了在FPGA内构建BIST控制器的方法,并介绍了FPGA自测试的实现以及在板级设计过程中要考虑的问题。The Boundary-scan technology and the BIST（Built-In Self Test） technology were developed for the board-level measurement problem of complex PCBs.According to the trend in development of board-level DFT（Design for Test）,the design strategy for board-level BIST based on FPGA is put forward in this paper.By descriting about the design of memory BIST and digital logic BIST and analog circuit BIST,the advantages of building BIST controller in FPGA are indicated.The configuration and self-test method are given in the end.And some issues that should be considered in the DFT process are introduced.

关 键 词：BIST 可测性 DFT FPGA 控制器 边界扫描 

分 类 号：TP274[自动化与计算机技术—检测技术与自动化装置]