片上逻辑分析仪的设计  

Design for on-chip Logic Analyzer

作　　者：张小林[1] 姜大力[1] 李华旺[1] 杨根庆[1] 

机构地区：[1]中国科学院上海微系统与信息技术研究所

出　　处：《计算机测量与控制》2008年第3期430-432,共3页Computer Measurement &Control

基　　金：上海市科委国际合作资助项目(052207046)

摘　　要：提出了一种用在FPGA上实现的片上逻辑分析仪的设计方案;随着FPGA的规模的增大,在其内部可以实现复杂的SoC设计,但是I/O端口数量有限,采用VHDL设计,可以在源代码级插入到设计中,这也使得它与FPGA的器件类型和开发软件保持独立,它可以对FPGA内部的任何信号和复杂的事件进行追踪,采样的结果保存在通过片上的同步RAM实现的循环跟踪缓存区,通过AMBAAPB总线接口完成对触发引擎控制和缓存区的读写;这种实现方案的逻辑分析仪占用资源小,可以达到的频率高,可广泛应用到基于AMBA总线的SoC设计中;最后,对可改进的方向进行了分析。Principles of an FPGA internal logic analyzer are presented.FPGA devices have grown larger and larger and can contain very complex SoC designs in a package with limited I/O resources.The analyzer code is written in VHDL and inserted into design at the source description level.This allows keeping the independent of used design software and FPGA architecture.It enables the designer to trace arbitrary signals inside the FPGA fabric and to trig on complex events.Samples are stored in a circular trace buffer implemented with synchronous on-chip RAM.Trigger engine control and trace buffer readout is done over an AMBA APB interface.It is shown that this kind of a logic analyzer is small enough to fit inside smaller modern FPGA and that is runs fast enough to be used in wide range of designs.In addition,possible improvements are described.

关 键 词：片上逻辑分析仪 APB 星载计算机 

分 类 号：TP216[自动化与计算机技术—检测技术与自动化装置]