一种超小型AES专用处理器的FPGA实现  

A Very Small FPGA Implementation of Application-Specific Instruction Processor for AES

作　　者：张巨英[1] 王和明[1] 

机构地区：[1]空军工程大学导弹学院,陕西三原713800

出　　处：《微电子学与计算机》2008年第4期165-168,共4页Microelectronics & Computer

摘　　要：提出一种基于FPGA的专用处理器设计.它是用于高级加密标准的超小面积设计,支持密钥扩展(现在设计为128位密钥),加密和解密.这个设计采用了完全的8位数据路径宽度,创新的字节替换电路和乘累加器结构,在最小规模的Xilinx Spartan II FPGA芯片XC2S15上实现了一个高级加密标准AES的专用处理器,使用了不到60%的资源.当时钟为70MHz时,可以达到平均加密解密吞吐量2.1Mb/s.主要应用在把低资源占用,低功耗作优先考虑的场合.This paper presents an application-specific instruction processor designs based on field-programmable gate array （FPGA）. It is a very low-arca design for the advanced encryption standard, which supports key expansion （currently programmed for a 128-bit key）, encipher and decipher. The design uses fully 8-bit datapath, novel circuit for SubBytes operation and multiply-accumulate architecture, and is implemented on the smallest available Xilinx Spartan Ⅱ FPGA （XC2S15）, utilizing less than 60% of the resources. The average encipher-decipher throughput is 2. 1 Mb/s when clocked at 70 MHz. The design has numerous applications where low area and low power are priorities.

关 键 词：高级加密标准(AES) 专用处理器(ASIP) FPGA 小面积 8位 

分 类 号：TP368[自动化与计算机技术—计算机系统结构]