Ultra-low power S-Boxes architecture for AES  

作　　者：XING Ji-peng ZOU Xue-cheng GUO Xu 

机构地区：[1]Research Center for VLSI and Systems, Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan 430074, China

出　　处：《The Journal of China Universities of Posts and Telecommunications》2008年第1期112-117,共6页中国邮电高校学报（英文版）

基　　金：the Hi-Tech Research and Development Program of China（2006AA01Z226）； HUST-SRF（2006Z011B）； Program for New Century Excellent Talents in University and the Natural Science Foundation of Hubei（2006ABA080）.

摘　　要：It is crucial to design energy-efficient advanced encryption standard （AES） cryptography for low power embedded systems powered by limited battery. Since the S-Boxes consume much of the total AES circuit power, an efficient approach to reducing the AES power consumption consists in reducing the S-Boxes power consumption. Among various implementations of S-Boxes, the most energy-efficient one is the decoder-switchencoder （DSE） architecture. In this paper, we refine the DSE architecture and propose one faster, more compact S-Boxes architecture of lower power： an improved and full-balanced DSE architecture. This architecture achieves low power consumption of 68 μW at 10 MHz using 0.25 ktm 1.SV UMC CMOS technology. Compared with the original DSE S-Boxes, it further reduces the delay, gate count and power consumption by 8%, 14% and 10% respect/vely. At the sane time, simulation results show that the improved DSE S-Boxes has the best performance among various S-Boxes architectures in terms of power-area product and power-delay product, and it is optimal for implementing low power AES cryptography.It is crucial to design energy-efficient advanced encryption standard （AES） cryptography for low power embedded systems powered by limited battery. Since the S-Boxes consume much of the total AES circuit power, an efficient approach to reducing the AES power consumption consists in reducing the S-Boxes power consumption. Among various implementations of S-Boxes, the most energy-efficient one is the decoder-switchencoder （DSE） architecture. In this paper, we refine the DSE architecture and propose one faster, more compact S-Boxes architecture of lower power： an improved and full-balanced DSE architecture. This architecture achieves low power consumption of 68 μW at 10 MHz using 0.25 ktm 1.SV UMC CMOS technology. Compared with the original DSE S-Boxes, it further reduces the delay, gate count and power consumption by 8%, 14% and 10% respect/vely. At the sane time, simulation results show that the improved DSE S-Boxes has the best performance among various S-Boxes architectures in terms of power-area product and power-delay product, and it is optimal for implementing low power AES cryptography.

关 键 词：AES S-Boxes DSE CRYPTOGRAPHY low power 

分 类 号：TN47[电子电信—微电子学与固体电子学] TN911