一种高速CMOS电荷泵锁相环设计  

Design of a high-speed CMOS CPPLL

作　　者：熊元新[1] 胡仕刚[1] 徐征[1] 

机构地区：[1]武汉大学电气工程学院,湖北武汉430072

出　　处：《电路与系统学报》2008年第2期109-111,共3页Journal of Circuits and Systems

基　　金：国家自然科学基金资助项目(50577046)

摘　　要：文章描述了一种高速CMOS电荷泵锁相环设计与仿真。电路设计基于TSMC 2.5V 0.25μm CMOS工艺。用Cadence Artist Analog对电路仿真的结果显示,用它可以实现快速锁定和较低的功耗。In this paper, design and simulation of a high-speed CMOS CPPLL are presented. The circuit design is realized in TSMC 2.5V 0.25μm CMOS technology. The results of the simulation of the circuit with Cadence Artist Analog shows that this circuit has a better performance of short lock up time and low power cost.

关 键 词：集成电路 锁相环 CMOS 

分 类 号：TN911.8[电子电信—通信与信息系统]