D类音频功放芯片输出级电路的设计  

Design output stage for ClassD audio amplifier chip

作　　者：刘伟[1] 邹月娴[1] 黄令华[1] 

机构地区：[1]北京大学深圳研究生院集成微系统科学工程与应用国家级重点实验室,深圳518055

出　　处：《中国集成电路》2008年第4期58-62,共5页China lntegrated Circuit

摘　　要：在D类功放中,输出功率管有比较大的容性负载,会严重影响芯片的输出效能,本文基于Win-bond0.5μ CMOS工艺设计了一种适用于D类音频功放的驱动电路,在前置驱动级加入时钟控制信号,实现逻辑控制功能;合理设置功率管输出的死区时间,避免了功率管的同时导通,提升了电路的工作效率、改善了总谐波失真(THD)和毛刺电压。In ClassD audio power amplifier, there is a large parasitic capacitor with output power mosfets, which will seriously affect the performance of the chip. Based on the process of Winbond05 μ CMOS, this paper presents a driver circuit for the ClassD audio power amplifier. In the predriver stage, the clock signal is added to achieve the function of control logic. The proper deadtime is set to avoid the power mosfets （ NMOS＆PMOS ） conduction at the same time, it will increase the efficiency of the circuit, with the improvement of the THD （ Total Harmonic Distortion ） and voltage spike.

关 键 词：D类音频功放 输出级 功率管 桥接负载 

分 类 号：TN722.75[电子电信—电路与系统]