A High Purity Integer-N Frequency Synthesizer in 0.35μm SiGe BiCMOS  

基于0.35μm SiGe BiCMOS的高纯度频率综合器(英文)

作　　者：张健[1] 李志强[1] 陈立强[1] 陈普峰[1] 张海英[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《Journal of Semiconductors》2008年第4期655-659,共5页半导体学报（英文版）

基　　金：国家自然科学基金项目(批准号:60276021);国家重点基础研究发展规划(批准号:G2002CB311901)资助项目~~

摘　　要：An integer-N frequency synthesizer in 0.35μm SiGe BiCMOS is presented. By implementing different building blocks with different types of devices,a high purity frequency synthesizer with excellent spur and phase noise performance has been realized. All the building blocks are implemented with differential topology except for the off-chip loop filter. To further reduce the phase noise,bonding wires are used to form the resonator in the LC-VCO. The frequency synthesizer operates from 2.39 to 2.72GHz with output power of about 0dBm. The measured closed-loop phase noise is - 95dBc/Hz at 100kHz offset and - 116dBc/Hz at 1MHz offset from the carrier. The power level of the reference spur is less than - 72dBc. With a 3V power supply, the whole chip including the output buffers consumes 60mA.介绍了一个基于0.35μm SiGe BiCMOS的整数N频率综合器.通过采用不同工艺来实现不同模块,实现了一个具有良好的杂散和相噪性能的高纯度频率综合器.除环路滤波器外所有的部件均采用差分电路结构.为了进一步减小相位噪声,压控振荡器中采用绑定线来形成谐振.该频率综合器可在2.39-2.72GHz的频率范围内输出功率0dBm.在100kHz频偏处测得的相位噪声为-95dBc/Hz,在1MHz频偏处测得的相位噪声为-116dBc/Hz.参考频率处杂散小于-72dBc.在3V的工作电压下,包括输出驱动级在内的整个芯片消耗60mA电流.

关 键 词：SiGe BiCMOS phase-locked loop high purity loop bandwidth 

分 类 号：TN74[电子电信—电路与系统]