频率综合器中低功耗高速多模分频器设计的“时间借用”方法  

A "Time Reuse" Technique for Design of a Low-Power,High-Speed Multi-Modulus Divider in a Frequency Synthesizer

作　　者：袁泉[1] 杨海钢[1] 董方源[1] 钟伦贵[1] 

机构地区：[1]中国科学院电子学研究所

出　　处：《Journal of Semiconductors》2008年第4期794-799,共6页半导体学报（英文版）

摘　　要：提出一种基于"时间借用"方法的相位切换型多模高速分频器,新型的相位切换控制策略有效地减少相位切换控制环路的延时,使得多模分频器在较低的电源电压下仍能在较高的输入频率下工作,同时获得最大可分频模数.本文设计的多模分频器采用0.35μm标准CMOS工艺流片.测试结果表明,该多模分频器能够在2.5V电源电压下对2.4GHz输入信号进行48到64分频,所消耗的最大功耗仅为4.85mW,与近来报道的CMOS多模分频器相比,进一步降低了功耗速度比.A low power,continuous phase-switching multi-modulus divider is proposed based on the ＂time reuse＂ method. The novel phase-switching control strategy significantly reduces the delay of the phase-switching control loop so that the multi-modulus divider can work with higher input frequency and obtain the maximum modulus for a low power supply. According to the measurement resuits,this multi-modulus divider can divide the 2, 4GHz input frequency by 48 up to 64 for a minimum power supply voltage of 2.5V in a 0.35μm CMOS process. The maximum power dissipation is only 4.85mW. Compared with other CMOS multi-modulus dividers reported recently,our design demonstrates a considerable improvement in .the power-to-speed ratio.

关 键 词：多模分频器 相位切换 低功耗 时间借用 

分 类 号：TN772[电子电信—电路与系统]