Viterbi译码器全并行IP核的研究与实现  

Research and realization of the parallel Viterbi decoder

作　　者：李伟[1] 余熙武[2] 金惠华[1] 尚利宏[1] 

机构地区：[1]北京航空航天大学计算机学院,北京100083 [2]北京航空工程技术研究中心,北京100076

出　　处：《电子测量技术》2008年第3期87-90,共4页Electronic Measurement Technology

摘　　要：在无线数传设备中,为了提高数据传输的可靠性,往往采用卷积编码。这就要用到Viterbi译码器,而市面上的国外厂商提供的IP核价格昂贵,且可移植性差,为此需要掌握核心技术,自主开发。本文介绍了Viterbi译码的原理及应用,对Viterbi译码的算法,实现结构进行了深入研究,提出了采用乒乓RAM全并行的译码方式。并对算法进行优化并用FPGA实现,采用QaurtusⅡ作为布线工具,同时用modelsim进行了综合后仿真,译码速度达到100 MHz,并且在要求的信噪比条件下,误码率和理论值吻合。During the wireless equipment, in order to improve the reliability of the data to translate, convolutional encoding are always used. Viterbi decoder is used, however the IP core is always very expensive offered by foreign manufactures in the market and the migration is bad, researching and designing the kernel technology by ourselves. In this paper , the theory and the application of Viterbi algorithm are explained , and study the structure of algorithm deeply , the ping-pong decode method is presented. The algorithm is implemented in FPGA, designed with Qaurtus Ⅱ and simulated with modelsim, the speed of decoding is up to 100 MHz, under certain signal to noise , the code error rate is near to the ideal value.

关 键 词：VITERBI 分支度量 加比选 回溯 全并行 

分 类 号：TN919.3[电子电信—通信与信息系统]