一种嵌入式DSP核的设计及FPGA验证  

Design and FPGA Verification of an Embedded DSP Core

作　　者：李辉[1] 李平[1] 

机构地区：[1]电子科技大学电子薄膜与集成器件国家重点实验室,成都610054

出　　处：《微电子学》2008年第2期302-305,共4页Microelectronics

摘　　要：设计了一个4级流水线的16位定点DSP核。该DSP核支持151条指令,除了执行返回指令需要两个机器周期外,其他指令都在一个机器周期内完成。该DSP核用Altera公司的Cy-clone EP1C12Q240C8 FPGA器件实现,可工作在18.6 MHz。基于Altera公司的FPGA集成开发环境QUARYUS II和FPGA开发板,对该DSP核进行了FPGA验证。结果表明,该DSP核能正确地执行各条指令,并能完成IMA ADPCM的编解码功能。A 16-bit fixed-point DSP core with 4 pipeline stages is proposed. The instruction set of the DSP contains 138 instructions, and all instructions take only one machine cycle except PdET instruction, where 2 cycles are necessary. The DSP core prototype was realized using Altera＇s EPIC12Q240C8 FPGA with operation frequency of 18. 6 MHz. Based on QUARTUS II software and FPGA hoard, the prototype was verified, which indicated that all instructions executed correctly and the codec function of IMA ADPCM was also realized as expected.

关 键 词：DSP核 FPGA RAW相关 IMA ADPCM 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]