一种基于CORDIC算法的高速高精度数字鉴相器  

A High-speed and High-accuracy Digital Phase Demodulator Based on CORDIC Algorithm

作　　者：严平[1] 汪学刚[1] 钱璐[1] 

机构地区：[1]电子科技大学电子工程学院,成都610054

出　　处：《电讯技术》2008年第4期76-79,共4页Telecommunication Engineering

摘　　要：提出了一种基于CORDIC算法的高速、高精度数字鉴相器。该数字鉴相器根据正交解调原理测相,采用高速全流水线结构在FPGA上实现,利用CORDIC算法实现了数字下变频(DDC)和相角的计算。本方法不需要正交本振信号与参考信号严格同步,并且允许输入信号的频率与DDC的NCO频率存在一定频偏,便于工程实现。经时序仿真验证,系统工作时钟可达100 MHz,在30 dB的信噪比条件下,测相误差小于0.004 rad,样本标准差小于0.03 rad。An improved structure of digital phase demodulator based on CORDIC algorithm is presented. Phas- shift is measured according to the principle of quadrature demodulation. Digital down convertion （DDC） and calculation of angle are realized by CORDIC algorithm. The local oscillation need not be synchronous with the reference signal, and the frequency of input signal is allowed to deviate from the frequency of NCO to a certain extent. Simulation with FPGA shows that phase - shift measurement is at high - speed and high- accuracy： it can work at 100MHz system clock, the error of phase demodulation is less than 0.004 rad, and the sample standard deviation is less than 0.03 rad when SNR is 30 dB.

关 键 词：正交解调 数字鉴相器 CORDIC算法 频偏 流水线结构 FPGA 

分 类 号：TN763.3[电子电信—电路与系统] TN953