高码速率QPSK解调器的设计  

Design of High-speed QPSK Demodulator

作　　者：杨东亮[1] 罗志强[1] 许家栋[1] 

机构地区：[1]西北工业大学电子信息学院,陕西西安710072

出　　处：《航空计算技术》2008年第2期104-106,共3页Aeronautical Computing Technique

摘　　要：对目前通信中急需的高码速率传输设备进行了研究,首先分析了硬判决环的工作原理和设计方法,并且以此算法为基础在硬件上实现了高达百兆QPSK解调器的设计。整个硬判决环的算法设计是基于Altera公司的QuartusII开发平台,并在CycloneII系列FPGA中实现。用FPGA实现硬判决算法具有体积小、功耗低、集成度高、可软件升级、扰干扰能力强的特点,符合未来通信技术发展的方向。而整套其它外围模块包括解调芯片、AD芯片、DA芯片、RF合成器等都是采用的非常高端的芯片来实现的。In the current communications it needs high- speed transmission equipment. This paper gives a introduction to the algorithm of Hard- decision. The design of algorithm is based on Altera＇s QuartusⅡ development platforms, and it has been achieved in CycloneⅡ. It has many advantages to use FPGA. For example：small size, low power, high integration and strong ability to interfere. It consistents with the future direction of the development of communications technology. And the entire peripheral modules include chip AD,chip DA and chip RF synthesizer,and so on are used in very high performance chip to achieve.

关 键 词：QPSK 高码速率 载波恢复 解调器 

分 类 号：TN923[电子电信—通信与信息系统]