一种雷达信号侦察处理器的设计与实现  

Design and Implementation of a Processor for Radar Signal Reconnaissance

作　　者：罗跃东[1] 陈禾[1] 王晓君[1] 

机构地区：[1]北京理工大学信息科学技术学院电子工程系,北京100081

出　　处：《北京理工大学学报》2008年第4期352-355,共4页Transactions of Beijing Institute of Technology

摘　　要：研究一种基于FFT/IFFT、全FPGA实现、环形结构的电子战数字接收机信号处理器.该处理器由4片FPGA分别实现高速数据传输接口、FFT/IFFT运算及信号的时/频域检测,FPGA以分布式、多总线、并行、流水方式工作.可检测最多4个同时到达的脉冲雷达信号的载波频率及脉冲描述字等参数,当采用256 K(1 K=1024)点的FFT变换3、2 K点的IFFT变换时,检测出4个信号的典型用时约20 ms.由一块板卡完成了数据的接收、运算和时频域信号检测等工作.Investigates a signal processor of electromic warefare（EW） digital receiver based on FFT/IFFT algorithm, and realized completely by FPGA constructed annularly. Four FPGAs implement respectively the high-speed data transmission interface, FFT/IFFT operation and signal detection in the time/frequency domain. The FPGAs run with distributed, multi-bus, parallel and pipeline mode. This processor can detect the parameters of carrier frequency and pulse description word for 4 simultaneous-arrival signals at most, and they need only about 20 ms to detect 4 signals while 256 K（1 K=1 024） point FFT and 32 K point IFFT are adopted. The data receiving, operating and signal detection in time/frequency domain are realized on a board.

关 键 词：数字接收机 信号处理器 现场可编程门阵列(FPGA) 快速傅里叶变换(FFT) 

分 类 号：TN911.72[电子电信—通信与信息系统]