低功耗可编程吞脉冲计数器设计  

Design of low power programmable pulse swallow counter

作　　者：金晶[1] 周健军[1] 莫亭亭[1] 

机构地区：[1]上海交通大学微电子学院,上海200240

出　　处：《信息技术》2008年第4期67-69,共3页Information Technology

摘　　要：介绍了一种基于0.18μm CMOS工艺的频率合成器子电路吞脉冲计数器的设计方法,并对电路功耗进行了优化。仿真结果表明,该计数器可与双模预分频器构成分频比连续变化的可变分频器,系统最高工作频率为7.5GHz,双模预分频器为采用相位切换结构的16/17预分频器,吞脉冲计数器部分最高工作频率为700MHz,电源电压2V,消耗电流小于0.4mA。The design of pulse swallow counter for frequency synthesizer fabricated in 0.18μm CMOS process is introduced and the power dissipation is optimized. Simulation results show that the proposed pulse swallow counter can cooperate with dual-modulus prescaler and realize continuous division ratio according to N, P and S. The maximum operating frequency of the whole system is 7.5GHz, and with the 16/17 phase-switching dual-modulus prescaler, the programmable pulse swallow counter demonstrates a maximum operating frequency of 700MHz, and the current is less than 0.4mA at 2V supply voltage.

关 键 词：吞脉冲计数器 频率综合器 低功耗 CMOS 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN722