数字电路门级并行逻辑模拟  

Digital circuit gate-level parallel logic simulation

作　　者：龙川[1] 宁涛[1] 

机构地区：[1]重庆大学计算机学院,重庆400030

出　　处：《计算机工程与应用》2008年第13期63-66,共4页Computer Engineering and Applications

摘　　要：对基于事件驱动的电路门级并行逻辑模拟算法和相应的电路划分算法进行了研究。在保守协议的基础上,模拟算法采用流水线技术避免了死锁;采用事件打包,消息队列和非阻塞通讯技术减少了消息传递开销。在聚集分解的基础上,电路划分算法对组合或时序电路都可进行非循环划分,保证流水线模拟不会出现死锁。在曙光集群上采用MPI实现了模拟算法,对ISCAS部分电路进行实验,获得了很好的加速比。最后提出采用预模拟方法的电路划分改进方案。Explore the algorithms of both the circuit gate-level parallel logic simulation based on event-driven and the corresponding circuit partition.On the conservative protocol ground,the pipeline simulation algorithm is used to solve deadlocks.For reducing the cost of messages passing,the event clumping,message queue and nonblocking communication techniques are applied. Based on the cluster decomposition,the acyclic partition for both combinational and sequential circuits is applied by the circuit partition algorithm,which guarantee no deadlock for pipeline-simulation.The simulation algorithm is implemented on Shuguang cluster by using MPI,and good speedup is obtained for the circuits in ISCAS benchmark suite.At last,the circuit partition improving method is proposed by applying the pre-simulation.

关 键 词：并行计算 门级逻辑模拟 事件驱动 消息队列 非循环电路划分 

分 类 号：TP391.76[自动化与计算机技术—计算机应用技术]