Robust CMOS phase frequency detector for high speed and low jitter charge pump PLL  

一种应用于高速低抖动电荷泵锁相环的高鲁棒性鉴频鉴相器(英文)

作　　者：周建政[1,2] 王志功[1] 

机构地区：[1]东南大学射频与光电集成电路研究所 [2]合肥工业大学计算机与信息学院,合肥230009

出　　处：《Journal of Southeast University(English Edition)》2008年第1期15-19,共5页东南大学学报（英文版）

摘　　要：In order to improve the performance of the existing phase frequency detectors （PFDs）, a systematical analysis of the existing PFDs is presented. Based on the circuit architecture, both classifications and comparisons are made. A new robust CMOS phase frequency detector for a high speed and low jitter charge pump phrase-locked loop （PLL） is designed. The proposed PFD consists of two rising-edge triggered dynamic D flip-flops, two positive-edge detectors and delaying units and two OR gates. It adopts two reset mechanisms to avoid the LIP and DN signals to be logic-1 simultaneously. Thus, any current mismatch of the charge pump circuit will not worsen the performance of the PLL. Furthermore, it has hardly any dead-zone phenomenon in phase characteristic. Simulations with ADS are performed based on a TSMC 0. 18-μm CMOS process with a 1.8-V supply voltage. According to the theoretical analyses and simulation results, the proposed PFD shows a satisfactory performance with a high operation frequency （≈ 1 GHz）, a wide phase-detection range [ ± 2π], a near zero dead-zone （ 〈 0. 1 ps）, high reliability, low phase jitter, low power consumption （ ≈100 μW） and small circuit complexity.为改善现有鉴频鉴相器(PFD)中存在的问题,从理论分析的角度对现有的PFD进行了研究,并对其进行了基于电路结构的分类与比较.提出并设计了一种应用于高速低抖动电荷泵锁相环的高鲁棒性新型鉴频鉴相器.该PFD由2个上升沿触发的动态D触发器、2个上升沿检测和延时模块及2个或门组成.由于融合了2种复位机制,能避免UP与DN信号同时为高电平,因此,电荷泵的电流失配将不会恶化PLL的性能.而且,该PFD的鉴相特性中几乎没有鉴相死区.设计及仿真是基于1·8V电源电压的TSMC0·18μm CMOS工艺.由理论推导和电路仿真可知,该PFD具有高工作频率(≈ 1GHz)、高可靠性、宽鉴相范围([±2π])、零死区(<0·1ps)、低抖动、低功耗(≈100μW)、低复杂度等特性.

关 键 词：phase frequency detectors DEAD-ZONE blind-zone phase characteristic frequency characteristic 

分 类 号：TN763[电子电信—电路与系统]