基于FPGA的新型浮点FFT处理器设计  

Design of a new floating-point FFT processor based on FPGA

作　　者：范展[1] 梁国龙[1] 刘洋[1] 

机构地区：[1]哈尔滨工程大学水声工程学院,黑龙江哈尔滨150001

出　　处：《电子技术应用》2008年第5期23-26,共4页Application of Electronic Technique

摘　　要：针对现有FFT算法结构复杂、难以并行扩展的问题,提出了一种改进的FFT算法,在此基础上设计了一种基于浮点运算的FFT处理器,并进行了仿真验证。结果表明,新算法大大简化了系统结构,减少了系统的硬件开销,非常容易并行实现,且显著提高了运算效率,完成一次N点的FFT运算只需要N/2个时钟,完全满足实时信号处理的要求。Aiming at the problem in the existing FFT algorithm structure, which is not only complex but difficult to realize parallel expansion, a way of improved FFT algorithm is proposed, and a new floating-point FFT processor is designed in this paper. Simulation based on the Modelsim has carried on. The results indicated that the new algorithm is able to simplify the system structure greatly, reduce hardware consumption, and is easy to carry out parallel realization. Completing a N-points FFT only needs N/2 clock periods, it can satisfy the requests of real-time signal processing.

关 键 词：改进的FFT算法 浮点运算 实时信号处理 

分 类 号：TN911.72[电子电信—通信与信息系统] TP332[电子电信—信息与通信工程]