直扩解调器锁相环设计  

Design of PLL in DS-SS Demodulation System

作　　者：邬婕鸣[1] 张辉[1] 强晔[1] 

机构地区：[1]西安电子科技大学通信工程学院,陕西西安710071

出　　处：《电子科技》2008年第5期26-29,共4页Electronic Science and Technology

摘　　要：在大多普勒频移与低信噪比的通信环境下,为了实现直扩解调器中的载波提取,建立了载波同步模型,重点对其中的锁相环进行环路参数设计,并通过仿真比较了在不同信噪比下,锁相环环路参数对系统的捕获时间以及跟踪精度等性能的影响,对结果进行分析并得出结论。To realize carrier acquisition in DS-SS demodulation system, the carrier synchronization model is established with large Doppler frequency offset and low SNR. Emphasis is laid on the design of phase-locked loop parameters, the influence of which on the capturing time and tracking performance is studied under different SNR through software simulation. Finally, the conclusion is made based on an analysis of the simulation resuits.

关 键 词：锁相环 多谱勒频移 低信噪比 直扩解调器 

分 类 号：TN911.8[电子电信—通信与信息系统]