基于WDDL和行波流水技术的抗功耗攻击高性能分组密码协处理器设计与实现  

Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor using WDDL and Wave-Pipelining

作　　者：童元满[1] 王志英[1] 戴葵[1] 陆洪毅[1] 石伟[1] 

机构地区：[1]国防科学技术大学计算机学院,长沙410073

出　　处：《计算机学报》2008年第5期827-834,共8页Chinese Journal of Computers

基　　金：国家自然科学基金(60706026)资助

摘　　要：该文结合WDDL逻辑和行波流水技术,给出了分组密码协处理器的设计方法和设计流程.该设计流程实现简单,最大限度地利用了现有的成熟EDA工具.这种协处理器不仅能有效抗功耗攻击,而且具有运算性能高和功耗低的优势.文中以DES算法为例,给出了基于WDDL和行波流水技术的协处理器.实验结果表明,文中给出的分组密码协处理器设计方法以一定的芯片面积为代价获得了抗功耗攻击的能力,具有高运算性能和低功耗的优势.Novel design method and design flow of block cipher is presented based on the WDDL （Wave Dynamic Differential Logic） and Wave-Pipelining techniques. This design flow utilized the current commercially available EDA tools to a large degree. The WDDL and wave-pipelining based coprocessor not only resists power analysis, but also achieves high performance and low power consumption in nature. According to the design flow, this paper implements a DES coprocessor. The simulation results show that the novel design method achieves high performance, low power consumption and power analysis resistant ability at the cost of chip area.

关 键 词：功耗攻击 WDDL 行波流水 分组密码算法 协处理器 高性能 设计流程 

分 类 号：TP331[自动化与计算机技术—计算机系统结构]