面积优化的正交DDS软核编译器设计与实现  

Design of an Area Efficient Quadrature DDS IP Compiler

作　　者：于金刚[1] 杜伟韬[1] 

机构地区：[1]中国传媒大学广播电视数字化工程中心,北京100024

出　　处：《电讯技术》2008年第5期36-39,共4页Telecommunication Engineering

基　　金：国家高技术研究发展计划(863计划)项目(2002AA11901015)

摘　　要：为了使直接数字频率合成器(DDS)的IP设计达到资源和效率的较好平衡,提高此类IP设计的灵活性和重用性,应用泰勒插值方法对ROM进行压缩,设计并实现了一种自动生成正交DDS软核的编译器。文中推导了正交DDS内部信号关键参数设定公式,描述了IP编译器的设计流程,给出了实验结果。To achieve a better balance between performance and circuit area in DDS IP core, also in consideration of the flexibility and reusability of IP design, Taylor interpolation technique is adopted to compress the ROM of DDS and an IP compiler is realized. The key algorithm of the signals in hardware architecture of quadrature DDS and the principle of HDL code auto generator are described in detail and the design results are provided as well.

关 键 词：直接数字频率合成器 泰勒插值 IP编译器 FPGA 面积优化 

分 类 号：TN74[电子电信—电路与系统] TN762