数字跳频快速同步方案设计与FPGA实现  

Design and FPGA Implementation of a Digital Fast Synchronization Scheme for FHSS

作　　者：李瑾[1] 赵明生[1] 赵花荣[1] 罗康生[1] 

机构地区：[1]清华大学电子工程系,北京100084

出　　处：《微计算机信息》2008年第14期169-170,176,共3页Control & Automation

基　　金：国家自然科学基金资助(60171037)

摘　　要：本文设计了一种全数字高效的跳频同步方法,详细介绍了其基于FPGA硬件平台的实现方案。此方案采用了快速出局捕获和计数跟踪的方法,并用VerilogHDL进行电路描述。后仿真验证表明,在信噪比为-12dB的情况下仍能在短时间内达到精确同步。该方案具有抗干扰能力强,捕获时间短,结构简单等优点,在跳频通信中具有广泛的应用前景。An full digital scheme of frequency synchronization for FHSS communication and its implementation on FPGA is introduced. Fast-out sliding capturing and counter-based tracing are applied. The synchronization performance is excellent even when SNR is less than -12dB. This solution achieves the best anti-jam performance and fast synchronization speed through a simple structure, and could be widly uhilized in many areas.

关 键 词：跳频 同步 FPGA 

分 类 号：TN914.41[电子电信—通信与信息系统]