基于FPGA的TDICCD驱动时序设计  

Design on Driving Generator Based on FPGA Technology for TDICCD camera

作　　者：黄美玲[1] 张伯珩[1] 边川平[1] 李露瑶[1] 

机构地区：[1]中国科学院西安光学精密机械研究所,西安710068

出　　处：《微计算机信息》2008年第14期174-176,共3页Control & Automation

基　　金：国家863-708基金资助项目(2002AA782011)

摘　　要：在分析TDICCD器件驱动时序关系的基础上,设计了可选积分级数的驱动时序发生器.作为卫星上的有效载荷,TDIC-CD成像系统可以根据不同的光照条件及探测分辨率的需求,选择不同积分级数,提高成像系统的灵敏度。选用现场可编程门阵列(FPGA)作为硬件设计平台,使用VHDL语言对驱动时序发生器进行硬件描述,采用QuartusⅡ对所设计的驱动时序发生器进行了仿真。系统测试结果表明,所研制的驱动时序发生器可以满足TDICCD驱动要求.Driving schedules have been examined in detail.The driving schedule generator with tunable series has been designed for TDICCD camera.As a load of satellite, TDICCD camera＇can select integration series and improve sensitivity, according to illumination and exploration resolution request. Field programmable gates array （FPGA）has been chosen as the hardware design platform, driving schedule generator has been described with VHDL.The designed generator has been successfully fulfilled system simulation with Quartus Ⅱ software.Experiments show that designed generator is suitable for the driving of the high resolutution TDICCD camera.

关 键 词：TDICCD 时序 现场可编程门阵列(FPGA) 

分 类 号：TN386.5[电子电信—物理电子学]