A 0.18μm Transmitter and Receiver with High Speed and Low Power  

一个0.18μm高速低功耗的发送和接收电路(英文)

作　　者：张锋[1] 冯伟[1] 崔浩[1] 杨袆[1] 黄令仪[1] 胡伟武[1] 

机构地区：[1]中国科学院计算技术研究所,北京100080

出　　处：《Journal of Semiconductors》2008年第5期836-840,共5页半导体学报（英文版）

基　　金：国家杰出青年基金(批准号:60325205);国家自然科学基金(批准号:60673146 ,60603049);国家高技术研究发展计划(批准号:2006AA010201)资助项目~~

摘　　要：This paper describes the design of a low voltage differential signal （LVDS） transmitter and receiver with high speed and low power for CPU, LCD, FPGA, and other fast links. In the proposed transmitter, a stable reference and a common mode feedback circuit are integrated into the LVDS drivers, which enable the transmitter to tolerate variations of process, temperature, and supply voltage. The proposed receiver implements a rail-to-rail amplifier architecture that allows a 1.6Gb/s transmission. The transmitter and receiver are implemented in HJ TC 3.3V,0. 18μm CMOS technology. The experimental results demonstrate that the transmitter and receiver reach 1.6Gb/s. The transmitter and receiver pad cells exhibit a power consumption of 35 and 6mW,respectively.提出了一种高速低功耗的低压差分接口电路,它可以应用于CPU,LCD,FPGA等需要高速接口的芯片中.在发送端,一个稳定的参考电压和共模反馈电路被应用于低压差分电路中,它使得发送端能够克服电源、温度以及工艺引起的波形变化.在接收端采用了轨到轨的放大器结构,它可以工作到1.6Gb/s .芯片设计加工采用的是0.18μm CMOS工艺,芯片测试结果表明,整个发送接收端数据传输速率可以达到1.6Gb/s ,同时发送和接收端的功耗分别是35和6 mW.

关 键 词：LVDS rail to rail low power 

分 类 号：TN492[电子电信—微电子学与固体电子学]