An Adaptive-Bandwidth CMOS PLL with Low Jitter and a Wide Tuning Range  

一种低抖动、宽调节范围的带宽自适应CMOS锁相环(英文)

作　　者：宋颖[1] 王源[1] 贾松 李宏义[1] 赵宝瑛[1] 吉利久[1] 

机构地区：[1]北京大学微电子学研究所,北京100871

出　　处：《Journal of Semiconductors》2008年第5期908-912,共5页半导体学报（英文版）

摘　　要：This paper presents a novel adaptive-bandwidth charge pump PLL with low jitter and a wide tuning range. With an adaptive bandwidth,the proposed PLL can scale its loop dynamics proportional to the output frequency and maintain optimal performance over its entire output range. In order to improve the jitter performance of the PLL,a matching tech- nique is employed in the charge pump,and a voltage-to-voltage converter is used to achieve a low gain VCO. The experimental chip was fabricated in a 0. 35μm CMOS process. The measured results show that the PLL has perfect jitter performance within its operating range from 200MHz to 1.1GHz.提出了一种低抖动、宽蒯节范围的带宽自适应CMOS锁相环．由于环路带宽可根据输入频率进行自动调节，电路性能可在整个工作频率范围内得到优化．为了进一步提高电路的抖动特性，在电荷泵电路中采用匹配技术，并在压控振荡器中应用电压-电压转换电路以减小压控振荡器的增益．芯片采用SMIC 0．35μm CMOS工艺加工．测试结果表明该锁相环电路可在200MHz～1．1GHz的输出频率范围内保持良好的抖动性能．

关 键 词：PLL adaptive bandwidth low jitter wide tuning range 

分 类 号：TN911.8[电子电信—通信与信息系统] TN492[电子电信—信息与通信工程]