一种基于衬底偏置技术的低压低功耗运算放大器设计  

Low Power Low Voltage OP-amp Using Bulk-biased Technique

作　　者：窦建华[1] 郭铭铭[1] 潘敏[1] 

机构地区：[1]合肥工业大学计算机与信息学院,安徽合肥230009

出　　处：《仪表技术》2008年第5期10-12,共3页Instrumentation Technology

摘　　要：讨论衬底偏置MOS管的工作原理,对其低压特性进行了分析和仿真。并基于CMOS衬底偏置技术,设计了两级CMOS运算放大器。在0.6μm CMOS工艺条件下,电路的各项性能指标采用Smart Spice进行模拟验证。模拟结果表明在在1.0V的低电源电压下,失调电压为457.4μV,开环差模电压增益约为68dB,单位增益带宽为2.3MHz,相位裕量为67.4°,且其功耗仅有35μW,仿真结果显示了衬底偏置技术用于超低压模拟电路设计的优势。The principles of bulk-biased MOSFET are discussed and its low voltage characteristic is analyzed and simulated. A novel two stages operational amplifier is described based on PMOS bulk-biased technique, Under 0.61μm CMOS technological condition, the performance index of its circuit is verified by using Smartspice. The results indicate that its power is 351μW, when the supply voltage is 1.0V, the offset voltage is 457.41μV, the open-loop differential gain of the op amp is up to 68dB, the unit gain bandwidth is 2.3MHz and the phase margin is 67.4°. The simulated results show that the design of ultra-low voltage analog circuits using bulk-biased is promising.

关 键 词：CMOS集成电路 低功耗 衬底偏置 运算放大器 

分 类 号：TN402[电子电信—微电子学与固体电子学]