一种高吞吐量MD5算法的FPGA实现  

A High Throughput FPGA Implementation of MD5 Algorithm

作　　者：刘凯[1] 车明[1] 秦存秀[1] 

机构地区：[1]天津大学电信学院计算机系,天津300072

出　　处：《微处理机》2008年第1期188-191,共4页Microprocessors

摘　　要：MD5数字摘要算法在网络安全的诸多方面都得到广泛的应用。由于其串行计算的特点,对MD5算法的加速并不像其它具有并行操作算法那样容易实现。提出了采用4级流水线的结构来提高MD5运算的吞吐量,可以提升至吉比特级。在设计中,参考了分布式存储模型的结构来实现低延迟、低资源消耗及更好的可扩展性。The MD5 message-digest algorithm is used widely in many application fields of network security. Because of its nature of sequential computation, acceleration on MD5 is not as easy as that on some other algorithms which have many parallel operations inside. This paper proposes 4 - stage pipelining architecture to increase throughput of the MD5 implementation to gigabit level. In the design, the distributedmemory model is adopted to provide lower latency, fewer logic resource requirement and better scalability.

关 键 词：MD5算法 现场可编辑逻辑门阵列 流水线 

分 类 号：TN47[电子电信—微电子学与固体电子学]