基于Verilog的并行前缀Ling型加法器的验证  

Verification of the Design of High-Speed Parallel-Prefix Ling Adders Based on Verilog HDL

作　　者：肖九思[1] 张磊 

机构地区：[1]福州大学物理与信息学院,福州350002 [2]福建三元达通讯股份有限公司,福州350002

出　　处：《计算机与数字工程》2008年第5期150-152,共3页Computer & Digital Engineering

基　　金：福建省重大科技专项(编号:2007HZ0003-1)资助;福州市高新技术产业化贷款贴息项目(编号:2007-D-006)资助

摘　　要：随着DSP处理器运算速度的大幅提高,为进一步提高运算速度,各种不同结构的加法器设计相继提出。其中并行前缀加法器以其简单的标准单元和规则的内部连接的结构特点,非常适合VLSI的实现。基于Verilog语言,对快速并行前缀Ling型加法器设计进行RTL级验证,并分析比较不同的验证方法。With the great increase of the speed of DSP processors,the various structural design of adders were proposed to improve the computational speed. Parallel - prefix adders, which are composed of simple normal units and regular interior connection, are well - suited for VLSI implementations. Verification methods for the design of high - speed parallel - prefix VLSI Ling adders based on Verilog HDL are introduced in the paper. The analyses compared with these different methods are also presented.

关 键 词：FPGA验证 并行前缀加法器 VERILOG语言 测试平台 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]